Design and Analysis of Cache Coherent Multistage Interconnection Networks.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/NandaB93
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/NandaB93
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Ashwini_K._Nanda
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Laxmi_N._Bhuyan
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foaf:
homepage
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http://dx.doi.org/doi.org%2F10.1109%2F12.214692
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DBLP journals/tc/NandaB93
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DOI doi.org%2F10.1109%2F12.214692
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issued
1993
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journal
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Design and Analysis of Cache Coherent Multistage Interconnection Networks.
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https://dblp.l3s.de/d2r/resource/authors/Ashwini_K._Nanda
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https://dblp.l3s.de/d2r/resource/authors/Laxmi_N._Bhuyan
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swrc:
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4
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pages
458-470
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dc:
subject
cache coherent multistage interconnection networks; multiple copy cache coherence protocol; multistage bus network; coherence traffic; simulation models; multiprocessor interconnection networks; performance evaluation; protocols.
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dc:
title
Design and Analysis of Cache Coherent Multistage Interconnection Networks.
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42
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