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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/NandaB93>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ashwini_K._Nanda>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Laxmi_N._Bhuyan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.214692>
foaf:homepage <https://doi.org/10.1109/12.214692>
dc:identifier DBLP journals/tc/NandaB93 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.214692 (xsd:string)
dcterms:issued 1993 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Design and Analysis of Cache Coherent Multistage Interconnection Networks. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ashwini_K._Nanda>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Laxmi_N._Bhuyan>
swrc:number 4 (xsd:string)
swrc:pages 458-470 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/NandaB93/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/NandaB93>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc42.html#NandaB93>
rdfs:seeAlso <https://doi.org/10.1109/12.214692>
dc:subject cache coherent multistage interconnection networks; multiple copy cache coherence protocol; multistage bus network; coherence traffic; simulation models; multiprocessor interconnection networks; performance evaluation; protocols. (xsd:string)
dc:title Design and Analysis of Cache Coherent Multistage Interconnection Networks. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 42 (xsd:string)