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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/PandaNDN99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alexandru_Nicolau>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Nakamura>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nikil_D._Dutt>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Preeti_Ranjan_Panda>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.752655>
foaf:homepage <https://doi.org/10.1109/12.752655>
dc:identifier DBLP journals/tc/PandaNDN99 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.752655 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alexandru_Nicolau>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Nakamura>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nikil_D._Dutt>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Preeti_Ranjan_Panda>
swrc:number 2 (xsd:string)
swrc:pages 142-149 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/PandaNDN99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/PandaNDN99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc48.html#PandaNDN99>
rdfs:seeAlso <https://doi.org/10.1109/12.752655>
dc:subject Loop tiling, data cache, data alignment, cache conflict. (xsd:string)
dc:title Augmenting Loop Tiling with Data Alignment for Improved Cache Performance. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 48 (xsd:string)