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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/ParkLKHY03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Il-San_Kim>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kil-Whan_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sung-Bong_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tack-Don_Han>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Woo-Chan_Park>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTC.2003.1244948>
foaf:homepage <https://doi.org/10.1109/TC.2003.1244948>
dc:identifier DBLP journals/tc/ParkLKHY03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTC.2003.1244948 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Il-San_Kim>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kil-Whan_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sung-Bong_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tack-Don_Han>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Woo-Chan_Park>
swrc:number 11 (xsd:string)
swrc:pages 1501-1508 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/ParkLKHY03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/ParkLKHY03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc52.html#ParkLKHY03>
rdfs:seeAlso <https://doi.org/10.1109/TC.2003.1244948>
dc:subject 3D graphics, graphics hardware, rendering hardware, pixel cache. (xsd:string)
dc:title An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 52 (xsd:string)