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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/PatelBB07a>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mohammed_Benaissa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Riyaz_A._Patel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Said_Boussakta>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTC.2007.70750>
foaf:homepage <https://doi.org/10.1109/TC.2007.70750>
dc:identifier DBLP journals/tc/PatelBB07a (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTC.2007.70750 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mohammed_Benaissa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Riyaz_A._Patel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Said_Boussakta>
swrc:number 11 (xsd:string)
swrc:pages 1484-1492 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/PatelBB07a/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/PatelBB07a>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc56.html#PatelBB07a>
rdfs:seeAlso <https://doi.org/10.1109/TC.2007.70750>
dc:subject Modulo 2n-1 adders, One's complement adders, parallel-prefix adders, computer arithmetic, VLSI design (xsd:string)
dc:title Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 56 (xsd:string)