High-Performance 3-1 Interlock Collapsing ALU's.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/PhillipsV94
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bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/PhillipsV94
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https://dblp.l3s.de/d2r/resource/authors/Stamatis_Vassiliadis
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DBLP journals/tc/PhillipsV94
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1994
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High-Performance 3-1 Interlock Collapsing ALU's.
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3
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257-268
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dc:
subject
reduced instruction set computing; digital arithmetic; parallel architectures; 3-1 interlock collapsing ALU; execution interlocks; Boolean equations; critical path; delay; CMOS technology; multiple instruction issuing machines.
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High-Performance 3-1 Interlock Collapsing ALU's.
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43
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