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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/PhillipsV94>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_Phillips>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Stamatis_Vassiliadis>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.272427>
foaf:homepage <https://doi.org/10.1109/12.272427>
dc:identifier DBLP journals/tc/PhillipsV94 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.272427 (xsd:string)
dcterms:issued 1994 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label High-Performance 3-1 Interlock Collapsing ALU's. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_Phillips>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Stamatis_Vassiliadis>
swrc:number 3 (xsd:string)
swrc:pages 257-268 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/PhillipsV94/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/PhillipsV94>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc43.html#PhillipsV94>
rdfs:seeAlso <https://doi.org/10.1109/12.272427>
dc:subject reduced instruction set computing; digital arithmetic; parallel architectures; 3-1 interlock collapsing ALU; execution interlocks; Boolean equations; critical path; delay; CMOS technology; multiple instruction issuing machines. (xsd:string)
dc:title High-Performance 3-1 Interlock Collapsing ALU's. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 43 (xsd:string)