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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/PomeranzR94a>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.312119>
foaf:homepage <https://doi.org/10.1109/12.312119>
dc:identifier DBLP journals/tc/PomeranzR94a (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.312119 (xsd:string)
dcterms:issued 1994 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Irith_Pomeranz>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sudhakar_M._Reddy>
swrc:number 9 (xsd:string)
swrc:pages 1100-1105 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/PomeranzR94a/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/PomeranzR94a>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc43.html#PomeranzR94a>
rdfs:seeAlso <https://doi.org/10.1109/12.312119>
dc:subject logic testing; sequential circuits; hardware reset; synchronous sequential circuit test generation; state variables; test sequence; test generation procedure. (xsd:string)
dc:title On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 43 (xsd:string)