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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/RoychowdhuryBK90>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jehoshua_Bruck>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thomas_Kailath>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vwani_P._Roychowdhury>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.54841>
foaf:homepage <https://doi.org/10.1109/12.54841>
dc:identifier DBLP journals/tc/RoychowdhuryBK90 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.54841 (xsd:string)
dcterms:issued 1990 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jehoshua_Bruck>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thomas_Kailath>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vwani_P._Roychowdhury>
swrc:number 4 (xsd:string)
swrc:pages 480-489 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/RoychowdhuryBK90/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/RoychowdhuryBK90>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc39.html#RoychowdhuryBK90>
rdfs:seeAlso <https://doi.org/10.1109/12.54841>
dc:subject reconfiguration; VLSI; WSI; reconfiguring processor arrays; faulty processors; flexible interconnection structure; array grid model; single-track switches; polynomial time algorithm; single-track model; fault tolerant computing; parallel processing; VLSI. (xsd:string)
dc:title Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 39 (xsd:string)