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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/SakiyamaBPV07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bart_Preneel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ingrid_Verbauwhede>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kazuo_Sakiyama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lejla_Batina>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTC.2007.1071>
foaf:homepage <https://doi.org/10.1109/TC.2007.1071>
dc:identifier DBLP journals/tc/SakiyamaBPV07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTC.2007.1071 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2n). (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bart_Preneel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ingrid_Verbauwhede>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kazuo_Sakiyama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lejla_Batina>
swrc:number 9 (xsd:string)
swrc:pages 1269-1282 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/SakiyamaBPV07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/SakiyamaBPV07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc56.html#SakiyamaBPV07>
rdfs:seeAlso <https://doi.org/10.1109/TC.2007.1071>
dc:subject Multiprocessor systems, processor architectures, reconfigurable hardware, arithmetic and logic units, public key cryptosystems. (xsd:string)
dc:title Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2n). (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 56 (xsd:string)