Enlarging Instruction Streams.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/SantanaRV07
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tc/SantanaRV07
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Alex_Ram%E2%88%9A%E2%89%A0rez
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Mateo_Valero
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Oliverio_J._Santana
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foaf:
homepage
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http://dx.doi.org/doi.org%2F10.1109%2FTC.2007.70742
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homepage
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https://doi.org/10.1109/TC.2007.70742
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dc:
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DBLP journals/tc/SantanaRV07
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dc:
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DOI doi.org%2F10.1109%2FTC.2007.70742
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dcterms:
issued
2007
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Enlarging Instruction Streams.
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https://dblp.l3s.de/d2r/resource/authors/Alex_Ram%E2%88%9A%E2%89%A0rez
>
foaf:
maker
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https://dblp.l3s.de/d2r/resource/authors/Mateo_Valero
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maker
<
https://dblp.l3s.de/d2r/resource/authors/Oliverio_J._Santana
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swrc:
number
10
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swrc:
pages
1342-1357
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owl:
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http://bibsonomy.org/uri/bibtexkey/journals/tc/SantanaRV07/dblp
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rdfs:
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https://doi.org/10.1109/TC.2007.70742
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dc:
subject
Superscalar processor design, instruction fetch, branch prediction, access latency, code optimization
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dc:
title
Enlarging Instruction Streams.
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56
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