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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/SapiechaJ90>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Krzysztof_Sapiecha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/R._Jarocki>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.61066>
foaf:homepage <https://doi.org/10.1109/12.61066>
dc:identifier DBLP journals/tc/SapiechaJ90 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.61066 (xsd:string)
dcterms:issued 1990 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Modular Architecture for High Performance Implementatin of the FFT Algorithm. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Krzysztof_Sapiecha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/R._Jarocki>
swrc:number 12 (xsd:string)
swrc:pages 1464-1468 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/SapiechaJ90/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/SapiechaJ90>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc39.html#SapiechaJ90>
rdfs:seeAlso <https://doi.org/10.1109/12.61066>
dc:subject modular architecture; high performance implementation; FRR algorithm; VLSI-oriented architecture; processing elements; single butterfly computation; built-in self-test; computer architecture; computerised signal processing; fast Fourier transforms; VLSI. (xsd:string)
dc:title Modular Architecture for High Performance Implementatin of the FFT Algorithm. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 39 (xsd:string)