Input Variable Assignment and Output Phase Optimization of PLA's.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/Sasao84
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/Sasao84
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Tsutomu_Sasao
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foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FTC.1984.1676349
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DBLP journals/tc/Sasao84
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DOI doi.org%2F10.1109%2FTC.1984.1676349
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dcterms:
issued
1984
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swrc:
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https://dblp.l3s.de/d2r/resource/journals/tc
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rdfs:
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Input Variable Assignment and Output Phase Optimization of PLA's.
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https://dblp.l3s.de/d2r/resource/authors/Tsutomu_Sasao
>
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10
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swrc:
pages
879-894
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rdfs:
seeAlso
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https://doi.org/10.1109/TC.1984.1676349
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dc:
subject
switching theory, Adder, complexity of logic circuits, decoder assignment, essential prime implicants, logic design, output phase optimization, programmable logic array
(xsd:string)
dc:
title
Input Variable Assignment and Output Phase Optimization of PLA's.
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33
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