Delay-Optimized Implementation of IEEE Floating-Point Addition.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/SeidelE04
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Delay-Optimized Implementation of IEEE Floating-Point Addition.
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dc:
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Floating-point addition, IEEE rounding, delay optimization, dual path algorithm, logical effort, optimized gate sizing, buffer insertion.
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Delay-Optimized Implementation of IEEE Floating-Point Addition.
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