Property | Value |
---|---|
dcterms:bibliographicCitation | <http://dblp.uni-trier.de/rec/bibtex/journals/tc/Singh88> |
dc:creator | <https://dblp.l3s.de/d2r/resource/authors/Adit_D._Singh> |
foaf:homepage | <http://dx.doi.org/doi.org%2F10.1109%2F12.8705> |
foaf:homepage | <https://doi.org/10.1109/12.8705> |
dc:identifier | DBLP journals/tc/Singh88 (xsd:string) |
dc:identifier | DOI doi.org%2F10.1109%2F12.8705 (xsd:string) |
dcterms:issued | 1988 (xsd:gYear) |
swrc:journal | <https://dblp.l3s.de/d2r/resource/journals/tc> |
rdfs:label | Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays. (xsd:string) |
foaf:maker | <https://dblp.l3s.de/d2r/resource/authors/Adit_D._Singh> |
swrc:number | 11 (xsd:string) |
swrc:pages | 1398-1410 (xsd:string) |
owl:sameAs | <http://bibsonomy.org/uri/bibtexkey/journals/tc/Singh88/dblp> |
owl:sameAs | <http://dblp.rkbexplorer.com/id/journals/tc/Singh88> |
rdfs:seeAlso | <http://dblp.uni-trier.de/db/journals/tc/tc37.html#Singh88> |
rdfs:seeAlso | <https://doi.org/10.1109/12.8705> |
dc:subject | wafer scale integration; area efficient fault tolerance scheme; large area VLSI processor arrays; interstitial sites; performance degradation; polynomial time algorithm; operational spares; area efficient layouts; switching network; reconfiguration; chip area utilization; interstitial redundancy; PE survival probabilities; cellular arrays; circuit layout; fault tolerant computing; redundancy; VLSI. (xsd:string) |
dc:title | Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays. (xsd:string) |
dc:type | <http://purl.org/dc/dcmitype/Text> |
rdf:type | swrc:Article |
rdf:type | foaf:Document |
swrc:volume | 37 (xsd:string) |