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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/SkadronAMC99>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Douglas_W._Clark>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kevin_Skadron>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Margaret_Martonosi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pritpal_S._Ahuja>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.811115>
foaf:homepage <https://doi.org/10.1109/12.811115>
dc:identifier DBLP journals/tc/SkadronAMC99 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.811115 (xsd:string)
dcterms:issued 1999 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Douglas_W._Clark>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kevin_Skadron>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Margaret_Martonosi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pritpal_S._Ahuja>
swrc:number 11 (xsd:string)
swrc:pages 1260-1281 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/SkadronAMC99/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/SkadronAMC99>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc48.html#SkadronAMC99>
rdfs:seeAlso <https://doi.org/10.1109/12.811115>
dc:subject Microarchitecture, trade-offs, branch prediction, cache, sampling, simulation, out-of-order execution, instruction window size, register-update unit. (xsd:string)
dc:title Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 48 (xsd:string)