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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/SmithP88>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andrew_R._Pleszkun>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_E._Smith>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.4607>
foaf:homepage <https://doi.org/10.1109/12.4607>
dc:identifier DBLP journals/tc/SmithP88 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.4607 (xsd:string)
dcterms:issued 1988 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Implementing Precise Interrupts in Pipelined Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andrew_R._Pleszkun>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_E._Smith>
swrc:number 5 (xsd:string)
swrc:pages 562-573 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/SmithP88/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/SmithP88>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc37.html#SmithP88>
rdfs:seeAlso <https://doi.org/10.1109/12.4607>
dc:subject precise recovery; pipelined processors; precise interrupt problem; saved process state; sequential model of program execution; architectural order; parallel pipeline structure; Cray-1S scalar architecture; performance degradation; interrupts; parallel architectures; performance evaluation; pipeline processing; system recovery. (xsd:string)
dc:title Implementing Precise Interrupts in Pipelined Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 37 (xsd:string)