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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/Sohi89>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gurindar_S._Sohi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.21141>
foaf:homepage <https://doi.org/10.1109/12.21141>
dc:identifier DBLP journals/tc/Sohi89 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.21141 (xsd:string)
dcterms:issued 1989 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gurindar_S._Sohi>
swrc:number 4 (xsd:string)
swrc:pages 484-492 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/Sohi89/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/Sohi89>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc38.html#Sohi89>
rdfs:seeAlso <https://doi.org/10.1109/12.21141>
dc:subject cache memory organization; yield; high performance VLSI processors; tolerance of defects faults; linear RAMs; trace-driven simulation analysis; performance degradation; buffer storage; fault location; integrated memory circuits; random-access storage; storage management chips; VLSI. (xsd:string)
dc:title Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 38 (xsd:string)