Extreme Area-Time Tradeoffs in VLSI.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/SuglaC90
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bibliographicCitation
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https://dblp.l3s.de/d2r/resource/authors/David_A._Carlson
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http://dx.doi.org/doi.org%2F10.1109%2F12.45210
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DBLP journals/tc/SuglaC90
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1990
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Extreme Area-Time Tradeoffs in VLSI.
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2
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251-257
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dc:
subject
layout; bounded fan-in; fan-out prefix computation graphs; area requirements; constant factor reduction; area-time tradeoff; carry look-ahead adder; lower bounds; circuit layout CAD; digital arithmetic; VLSI.
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Extreme Area-Time Tradeoffs in VLSI.
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39
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