[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/TahaW08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/D._Scott_Wills>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tarek_M._Taha>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTC.2007.70817>
foaf:homepage <https://doi.org/10.1109/TC.2007.70817>
dc:identifier DBLP journals/tc/TahaW08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTC.2007.70817 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label An Instruction Throughput Model of Superscalar Processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/D._Scott_Wills>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tarek_M._Taha>
swrc:number 3 (xsd:string)
swrc:pages 389-403 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/TahaW08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/TahaW08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc57.html#TahaW08>
rdfs:seeAlso <https://doi.org/10.1109/TC.2007.70817>
dc:subject Modeling of computer architecture, Pipeline processors, Modeling techniques (xsd:string)
dc:title An Instruction Throughput Model of Superscalar Processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 57 (xsd:string)