High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/TakagiYY85
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https://dblp.l3s.de/d2r/resource/authors/Shuzo_Yajima
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1985
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High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.
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9
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swrc:
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789-796
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dc:
subject
VLSI, Arithmetic operations, binary integer multiplication, carry-propagation-free adder, hardware algorithm, high-speed multiplier, redundant binary representation, signed-digit number representation
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dc:
title
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.
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34
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