A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/TaoHL92
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1992
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A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay.
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7
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totally self-checking checker; 1-out-of-N code; minimum gate delay; translator; NOR array; NOR-NOR PLA; delays; error detection codes; fault tolerant computing; logic arrays; logic design; logic testing.
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A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay.
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