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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/ThuauS88>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gabriele_Saucier>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ghislaine_Thuau>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.75140>
foaf:homepage <https://doi.org/10.1109/12.75140>
dc:identifier DBLP journals/tc/ThuauS88 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.75140 (xsd:string)
dcterms:issued 1988 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Optimized Layout of MOS Cells. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gabriele_Saucier>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ghislaine_Thuau>
swrc:number 1 (xsd:string)
swrc:pages 79-87 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/ThuauS88/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/ThuauS88>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc37.html#ThuauS88>
rdfs:seeAlso <https://doi.org/10.1109/12.75140>
dc:subject optimised MOS cell layout; logical optimization; optimized topological arrangements; minimized Boolean function; well-structured network; transistor merging procedure; nonseries-parallel network; circuit layout CAD; field effect integrated circuits; logic design; minimisation of switching nets. (xsd:string)
dc:title Optimized Layout of MOS Cells. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 37 (xsd:string)