Optimized Layout of MOS Cells.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/ThuauS88
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/ThuauS88
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Gabriele_Saucier
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https://dblp.l3s.de/d2r/resource/authors/Ghislaine_Thuau
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http://dx.doi.org/doi.org%2F10.1109%2F12.75140
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DBLP journals/tc/ThuauS88
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DOI doi.org%2F10.1109%2F12.75140
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dcterms:
issued
1988
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Optimized Layout of MOS Cells.
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https://dblp.l3s.de/d2r/resource/authors/Gabriele_Saucier
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https://dblp.l3s.de/d2r/resource/authors/Ghislaine_Thuau
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swrc:
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1
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79-87
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rdfs:
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dc:
subject
optimised MOS cell layout; logical optimization; optimized topological arrangements; minimized Boolean function; well-structured network; transistor merging procedure; nonseries-parallel network; circuit layout CAD; field effect integrated circuits; logic design; minimisation of switching nets.
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dc:
title
Optimized Layout of MOS Cells.
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37
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