Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/TirumalaiB91
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1991
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Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.
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dc:
subject
minimisation algorithms; multiple-valued programmable logic arrays; performance; heuristic algorithms; multiple-valued functions; charge-coupled device; CMOS; sum-of products; MIN operation; random-symmetric functions; tree search; backtracking; constrained implicant sets; charge-coupled device circuits; CMOS integrated circuits; logic arrays; many-valued logics; minimisation.
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Minimization Algorithms for Multiple-Valued Programmable Logic Arrays.
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