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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/Tyagi93>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Akhilesh_Tyagi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.257703>
foaf:homepage <https://doi.org/10.1109/12.257703>
dc:identifier DBLP journals/tc/Tyagi93 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.257703 (xsd:string)
dcterms:issued 1993 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label A Reduced-Area Scheme for Carry-Select Adders. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Akhilesh_Tyagi>
swrc:number 10 (xsd:string)
swrc:pages 1163-1170 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/Tyagi93/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/Tyagi93>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc42.html#Tyagi93>
rdfs:seeAlso <https://doi.org/10.1109/12.257703>
dc:subject reduced-area; carry-select adders; conditional-sum adders; carry-chain evaluations; gate-count; gate-delay; analytic evaluation; carry-ripple; classical carry-select; carry-skip adders; parallel-prefix adders; area-efficient; adders; logic circuits; logic design. (xsd:string)
dc:title A Reduced-Area Scheme for Carry-Select Adders. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 42 (xsd:string)