A Systolic Power-Sum Circuit for GF(2^m). | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/tc/Wei94>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Shyue-Win_Wei>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2F12.262128>
foaf:homepage	<https://doi.org/10.1109/12.262128>
dc:identifier	DBLP journals/tc/Wei94 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2F12.262128 (xsd:string)
dcterms:issued	1994 (xsd:gYear)
swrc:journal	<https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label	A Systolic Power-Sum Circuit for GF(2^m). (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Shyue-Win_Wei>
swrc:number	2 (xsd:string)
swrc:pages	226-229 (xsd:string)
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/journals/tc/Wei94/dblp>
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/tc/tc43.html#Wei94>
rdfs:seeAlso	<https://doi.org/10.1109/12.262128>
dc:subject	systolic arrays; error correction codes; logic gates; logic circuits; systolic power-sum circuit; finite field; logical gates; power-sum circuit; error-correcting codes; decoding. (xsd:string)
dc:title	A Systolic Power-Sum Circuit for GF(2^m). (xsd:string)
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rdf:type	swrc:Article
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swrc:volume	43 (xsd:string)