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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/WeiT90>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Belle_W._Y._Wei>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Clark_D._Thompson>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.53579>
foaf:homepage <https://doi.org/10.1109/12.53579>
dc:identifier DBLP journals/tc/WeiT90 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.53579 (xsd:string)
dcterms:issued 1990 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Area-Time Optimal Adder Design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Belle_W._Y._Wei>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Clark_D._Thompson>
swrc:number 5 (xsd:string)
swrc:pages 666-675 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/WeiT90/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/WeiT90>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc39.html#WeiT90>
rdfs:seeAlso <https://doi.org/10.1109/12.53579>
dc:subject area-time optimal adder design; VLSI parallel adder; modular design; component cells; static CMOS; dynamic programming; floating-point processor; 66 bit; adders; CMOS integrated circuits; digital arithmetic; dynamic programming; logic design; VLSI. (xsd:string)
dc:title Area-Time Optimal Adder Design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 39 (xsd:string)