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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/WonSE90>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sartaj_Sahni>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yacoub_M._El-Ziq>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Youngju_Won>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.46291>
foaf:homepage <https://doi.org/10.1109/12.46291>
dc:identifier DBLP journals/tc/WonSE90 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.46291 (xsd:string)
dcterms:issued 1990 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label A Hardware Accelerator for Maze Routing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sartaj_Sahni>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yacoub_M._El-Ziq>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Youngju_Won>
swrc:number 1 (xsd:string)
swrc:pages 141-145 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/WonSE90/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/WonSE90>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc39.html#WonSE90>
rdfs:seeAlso <https://doi.org/10.1109/12.46291>
dc:subject banked memory; hardware accelerator; maze routing; three-stage pipelines; circuit layout CAD. (xsd:string)
dc:title A Hardware Accelerator for Maze Routing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 39 (xsd:string)