A Hardware Accelerator for Maze Routing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/WonSE90
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/WonSE90
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Sartaj_Sahni
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Yacoub_M._El-Ziq
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Youngju_Won
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foaf:
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http://dx.doi.org/doi.org%2F10.1109%2F12.46291
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DBLP journals/tc/WonSE90
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DOI doi.org%2F10.1109%2F12.46291
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dcterms:
issued
1990
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swrc:
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label
A Hardware Accelerator for Maze Routing.
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1
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141-145
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dc:
subject
banked memory; hardware accelerator; maze routing; three-stage pipelines; circuit layout CAD.
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A Hardware Accelerator for Maze Routing.
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39
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