Simulation of a Word Recognition System on Two Parallel Architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/YoderJ89
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/YoderJ89
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Leah_H._Jamieson
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Mark_A._Yoder
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foaf:
homepage
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http://dx.doi.org/doi.org%2F10.1109%2F12.29466
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DBLP journals/tc/YoderJ89
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DOI doi.org%2F10.1109%2F12.29466
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issued
1989
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Simulation of a Word Recognition System on Two Parallel Architectures.
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https://dblp.l3s.de/d2r/resource/authors/Leah_H._Jamieson
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swrc:
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9
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swrc:
pages
1269-1284
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dc:
subject
word recognition system; parallel architectures; SIMD; VLSI processor array; parallel algorithms; simulations; 8-MHz MC68000; 12-MHz Intel 8051; digital simulation; parallel algorithms; parallel architectures; speech recognition.
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dc:
title
Simulation of a Word Recognition System on Two Parallel Architectures.
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38
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