Modeling and extraction of interconnect capacitances for multilayer VLSI circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tcad/AroraRSR96
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tcad/AroraRSR96
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kartik_V._Raol
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Llanda_M._Richardson
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Narain_D._Arora
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Reinhard_Schumann
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2F43.486272
>
foaf:
homepage
<
https://doi.org/10.1109/43.486272
>
dc:
identifier
DBLP journals/tcad/AroraRSR96
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2F43.486272
(xsd:string)
dcterms:
issued
1996
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/tcad
>
rdfs:
label
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kartik_V._Raol
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Llanda_M._Richardson
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Narain_D._Arora
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Reinhard_Schumann
>
swrc:
number
1
(xsd:string)
swrc:
pages
58-67
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/tcad/AroraRSR96/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/tcad/AroraRSR96
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/tcad/tcad15.html#AroraRSR96
>
rdfs:
seeAlso
<
https://doi.org/10.1109/43.486272
>
dc:
title
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
15
(xsd:string)