Clock skew reduction in ASIC logic design: a methodology for clock tree management.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tcad/BalboniCPQS98
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1998
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Clock skew reduction in ASIC logic design: a methodology for clock tree management.
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Clock skew reduction in ASIC logic design: a methodology for clock tree management.
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