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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/BinkleyHTMRF03>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Brian_C._Moss>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._E._Hopper>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_Foty>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_M._Binkley>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_M._Rochelle>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Steve_D._Tucker>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2002.806606>
foaf:homepage <https://doi.org/10.1109/TCAD.2002.806606>
dc:identifier DBLP journals/tcad/BinkleyHTMRF03 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2002.806606 (xsd:string)
dcterms:issued 2003 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label A CAD methodology for optimizing transistor current and sizing in analog CMOS design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Brian_C._Moss>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._E._Hopper>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_Foty>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_M._Binkley>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_M._Rochelle>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Steve_D._Tucker>
swrc:number 2 (xsd:string)
swrc:pages 225-237 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/BinkleyHTMRF03/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/BinkleyHTMRF03>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad22.html#BinkleyHTMRF03>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2002.806606>
dc:title A CAD methodology for optimizing transistor current and sizing in analog CMOS design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 22 (xsd:string)