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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/CabodiCPPV19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Danilo_Vendraminetto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gianpiero_Cabodi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marco_Palena>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paolo_Camurati>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paolo_Pasini>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2018.2808229>
foaf:homepage <https://doi.org/10.1109/TCAD.2018.2808229>
dc:identifier DBLP journals/tcad/CabodiCPPV19 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2018.2808229 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Logic Synthesis for Interpolant Circuit Compaction. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Danilo_Vendraminetto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gianpiero_Cabodi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marco_Palena>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paolo_Camurati>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paolo_Pasini>
swrc:number 2 (xsd:string)
swrc:pages 380-384 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/CabodiCPPV19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/CabodiCPPV19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad38.html#CabodiCPPV19>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2018.2808229>
dc:title Logic Synthesis for Interpolant Circuit Compaction. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 38 (xsd:string)