A timing-driven pseudoexhaustive testing for VLSI circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tcad/ChangR01
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https://dblp.l3s.de/d2r/resource/authors/Shih-Chieh_Chang
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2001
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A timing-driven pseudoexhaustive testing for VLSI circuits.
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A timing-driven pseudoexhaustive testing for VLSI circuits.
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