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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/ChouW97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jacob_K._White_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mike_Chou>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F43.664228>
foaf:homepage <https://doi.org/10.1109/43.664228>
dc:identifier DBLP journals/tcad/ChouW97 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F43.664228 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Efficient formulation and model-order reduction for the transient simulation of three-dimensional VLSI interconnect. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jacob_K._White_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mike_Chou>
swrc:number 12 (xsd:string)
swrc:pages 1454-1476 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/ChouW97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/ChouW97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad16.html#ChouW97>
rdfs:seeAlso <https://doi.org/10.1109/43.664228>
dc:title Efficient formulation and model-order reduction for the transient simulation of three-dimensional VLSI interconnect. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 16 (xsd:string)