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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/DabiriNMPS08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ani_Nahapetian>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Foad_Dabiri>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Majid_Sarrafzadeh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Miodrag_Potkonjak>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tammara_Massey>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2008.2003268>
foaf:homepage <https://doi.org/10.1109/TCAD.2008.2003268>
dc:identifier DBLP journals/tcad/DabiriNMPS08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2008.2003268 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ani_Nahapetian>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Foad_Dabiri>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Majid_Sarrafzadeh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Miodrag_Potkonjak>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tammara_Massey>
swrc:number 10 (xsd:string)
swrc:pages 1788-1797 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/DabiriNMPS08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/DabiriNMPS08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad27.html#DabiriNMPS08>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2008.2003268>
dc:title General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 27 (xsd:string)