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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/DattaBMR06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Animesh_Datta>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Saibal_Mukhopadhyay>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Swarup_Bhunia>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2006.873886>
foaf:homepage <https://doi.org/10.1109/TCAD.2006.873886>
dc:identifier DBLP journals/tcad/DattaBMR06 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2006.873886 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Animesh_Datta>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kaushik_Roy_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Saibal_Mukhopadhyay>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Swarup_Bhunia>
swrc:number 11 (xsd:string)
swrc:pages 2427-2436 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/DattaBMR06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/DattaBMR06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad25.html#DattaBMR06>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2006.873886>
dc:title Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 25 (xsd:string)