Generic linear RC delay modeling for digital CMOS circuits. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/tcad/DengS90>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/An-Chang_Deng>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Yan-Chyuan_Shiau>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2F43.45868>
foaf:homepage	<https://doi.org/10.1109/43.45868>
dc:identifier	DBLP journals/tcad/DengS90 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2F43.45868 (xsd:string)
dcterms:issued	1990 (xsd:gYear)
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rdfs:label	Generic linear RC delay modeling for digital CMOS circuits. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/An-Chang_Deng>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Yan-Chyuan_Shiau>
swrc:number	4 (xsd:string)
swrc:pages	367-376 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/tcad/tcad9.html#DengS90>
rdfs:seeAlso	<https://doi.org/10.1109/43.45868>
dc:title	Generic linear RC delay modeling for digital CMOS circuits. (xsd:string)
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swrc:volume	9 (xsd:string)