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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/DeschachtRAA93>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Daniel_Auvergne>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Denis_Deschacht>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michel_Robert>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nadine_Az%E2%88%9A%C2%A9mard-Crestani>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F43.238609>
foaf:homepage <https://doi.org/10.1109/43.238609>
dc:identifier DBLP journals/tcad/DeschachtRAA93 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F43.238609 (xsd:string)
dcterms:issued 1993 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Post-layout timing simulation of CMOS circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Daniel_Auvergne>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Denis_Deschacht>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michel_Robert>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nadine_Az%E2%88%9A%C2%A9mard-Crestani>
swrc:number 8 (xsd:string)
swrc:pages 1170-1177 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/DeschachtRAA93/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/DeschachtRAA93>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad12.html#DeschachtRAA93>
rdfs:seeAlso <https://doi.org/10.1109/43.238609>
dc:title Post-layout timing simulation of CMOS circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 12 (xsd:string)