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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/FujiwaraIYO08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chia_Yee_Ooi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hideo_Fujiwara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroyuki_Iwata>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tomokazu_Yoneda>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2008.927757>
foaf:homepage <https://doi.org/10.1109/TCAD.2008.927757>
dc:identifier DBLP journals/tcad/FujiwaraIYO08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2008.927757 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chia_Yee_Ooi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hideo_Fujiwara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroyuki_Iwata>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tomokazu_Yoneda>
swrc:number 9 (xsd:string)
swrc:pages 1535-1544 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/FujiwaraIYO08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/FujiwaraIYO08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad27.html#FujiwaraIYO08>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2008.927757>
dc:title A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 27 (xsd:string)