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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/HuangRRJ05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anand_Raghunathan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chao_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Niraj_K._Jha>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srivaths_Ravi_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2005.852276>
foaf:homepage <https://doi.org/10.1109/TCAD.2005.852276>
dc:identifier DBLP journals/tcad/HuangRRJ05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2005.852276 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Generation of distributed logic-memory architectures through high-level synthesis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anand_Raghunathan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chao_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Niraj_K._Jha>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srivaths_Ravi_0001>
swrc:number 11 (xsd:string)
swrc:pages 1694-1711 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/HuangRRJ05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/HuangRRJ05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad24.html#HuangRRJ05>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2005.852276>
dc:title Generation of distributed logic-memory architectures through high-level synthesis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 24 (xsd:string)