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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/LeeHLK23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Donghyun_Han>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sooryeong_Lee>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sungho_Kang_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Youngkwang_Lee>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2022.3172058>
foaf:homepage <https://doi.org/10.1109/TCAD.2022.3172058>
dc:identifier DBLP journals/tcad/LeeHLK23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2022.3172058 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Donghyun_Han>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sooryeong_Lee>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sungho_Kang_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Youngkwang_Lee>
swrc:number 1 (xsd:string)
swrc:pages 308-321 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/LeeHLK23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/LeeHLK23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad42.html#LeeHLK23>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2022.3172058>
dc:title Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 42 (xsd:string)