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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/LiLCP08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiayong_Le>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lawrence_T._Pileggi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mustafa_Celik>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xin_Li_0001>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2008.923241>
foaf:homepage <https://doi.org/10.1109/TCAD.2008.923241>
dc:identifier DBLP journals/tcad/LiLCP08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2008.923241 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiayong_Le>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lawrence_T._Pileggi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mustafa_Celik>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xin_Li_0001>
swrc:number 6 (xsd:string)
swrc:pages 1041-1054 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/LiLCP08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/LiLCP08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad27.html#LiLCP08>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2008.923241>
dc:title Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 27 (xsd:string)