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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/LoweG98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kerry_S._Lowe>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/P._Glenn_Gulak>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F43.703932>
foaf:homepage <https://doi.org/10.1109/43.703932>
dc:identifier DBLP journals/tcad/LoweG98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F43.703932 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kerry_S._Lowe>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/P._Glenn_Gulak>
swrc:number 5 (xsd:string)
swrc:pages 419-434 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/LoweG98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/LoweG98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad17.html#LoweG98>
rdfs:seeAlso <https://doi.org/10.1109/43.703932>
dc:title A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 17 (xsd:string)