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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/MaDWS89>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alberto_L._Sangiovanni-Vincentelli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hi-Keung_Tony_Ma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ruey-Sing_Wei>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Devadas>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F43.21836>
foaf:homepage <https://doi.org/10.1109/43.21836>
dc:identifier DBLP journals/tcad/MaDWS89 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F43.21836 (xsd:string)
dcterms:issued 1989 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Logic verification algorithms and their parallel implementation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alberto_L._Sangiovanni-Vincentelli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hi-Keung_Tony_Ma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ruey-Sing_Wei>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Srinivas_Devadas>
swrc:number 2 (xsd:string)
swrc:pages 181-189 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/MaDWS89/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/MaDWS89>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad8.html#MaDWS89>
rdfs:seeAlso <https://doi.org/10.1109/43.21836>
dc:title Logic verification algorithms and their parallel implementation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 8 (xsd:string)