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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/MalikSBS93>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alberto_L._Sangiovanni-Vincentelli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kanwar_Jit_Singh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Robert_K._Brayton>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sharad_Malik>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F43.277605>
foaf:homepage <https://doi.org/10.1109/43.277605>
dc:identifier DBLP journals/tcad/MalikSBS93 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F43.277605 (xsd:string)
dcterms:issued 1993 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alberto_L._Sangiovanni-Vincentelli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kanwar_Jit_Singh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Robert_K._Brayton>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sharad_Malik>
swrc:number 5 (xsd:string)
swrc:pages 568-578 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/MalikSBS93/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/MalikSBS93>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad12.html#MalikSBS93>
rdfs:seeAlso <https://doi.org/10.1109/43.277605>
dc:title Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 12 (xsd:string)