Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Zvonko_G._Vranesic>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2006.882119>
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dc:title	Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. (xsd:string)
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