A logic-to-logic comparator for VLSI layout verification. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Alexander_D._Schapira>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Peter_M._Maurer>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2F43.3221>
foaf:homepage	<https://doi.org/10.1109/43.3221>
dc:identifier	DBLP journals/tcad/MaurerS88 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2F43.3221 (xsd:string)
dcterms:issued	1988 (xsd:gYear)
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rdfs:label	A logic-to-logic comparator for VLSI layout verification. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Alexander_D._Schapira>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Peter_M._Maurer>
swrc:number	8 (xsd:string)
swrc:pages	897-907 (xsd:string)
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/journals/tcad/MaurerS88/dblp>
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/tcad/tcad7.html#MaurerS88>
rdfs:seeAlso	<https://doi.org/10.1109/43.3221>
dc:title	A logic-to-logic comparator for VLSI layout verification. (xsd:string)
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