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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/MirchandaniZAOS23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Aatmesh_Shrivastava>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marvin_Onabajo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Nikita_Mirchandani>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Safaa_A._Abdelfattah>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuqing_Zhang_0004>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2022.3170248>
foaf:homepage <https://doi.org/10.1109/TCAD.2022.3170248>
dc:identifier DBLP journals/tcad/MirchandaniZAOS23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2022.3170248 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Modeling and Simulation of Circuit-Level Nonidealities for an Analog Computing Design Approach With Application to EEG Feature Extraction. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Aatmesh_Shrivastava>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marvin_Onabajo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Nikita_Mirchandani>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Safaa_A._Abdelfattah>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuqing_Zhang_0004>
swrc:number 1 (xsd:string)
swrc:pages 229-242 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/MirchandaniZAOS23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/MirchandaniZAOS23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad42.html#MirchandaniZAOS23>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2022.3170248>
dc:title Modeling and Simulation of Circuit-Level Nonidealities for an Analog Computing Design Approach With Application to EEG Feature Extraction. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 42 (xsd:string)