Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tcad/PotkonjakDR95a
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dcterms:
bibliographicCitation
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https://dblp.l3s.de/d2r/resource/authors/Miodrag_Potkonjak
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https://dblp.l3s.de/d2r/resource/authors/Rabindra_K._Roy
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dcterms:
issued
1995
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Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.
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swrc:
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9
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swrc:
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1141-1154
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Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.
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