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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/QianPP94>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jessica_Qian>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lawrence_T._Pillage>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Satyamurthy_Pullela>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F43.331409>
foaf:homepage <https://doi.org/10.1109/43.331409>
dc:identifier DBLP journals/tcad/QianPP94 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F43.331409 (xsd:string)
dcterms:issued 1994 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jessica_Qian>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lawrence_T._Pillage>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Satyamurthy_Pullela>
swrc:number 12 (xsd:string)
swrc:pages 1526-1535 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/QianPP94/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/QianPP94>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad13.html#QianPP94>
rdfs:seeAlso <https://doi.org/10.1109/43.331409>
dc:title Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 13 (xsd:string)