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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tcad/ReeseTTH05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Cherrice_Traver>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/David_Hemmendinger>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mitchell_A._Thornton>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Robert_B._Reese>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTCAD.2005.844084>
foaf:homepage <https://doi.org/10.1109/TCAD.2005.844084>
dc:identifier DBLP journals/tcad/ReeseTTH05 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTCAD.2005.844084 (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tcad>
rdfs:label Early evaluation for performance enhancement in phased logic. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Cherrice_Traver>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/David_Hemmendinger>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mitchell_A._Thornton>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Robert_B._Reese>
swrc:number 4 (xsd:string)
swrc:pages 532-550 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tcad/ReeseTTH05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tcad/ReeseTTH05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tcad/tcad24.html#ReeseTTH05>
rdfs:seeAlso <https://doi.org/10.1109/TCAD.2005.844084>
dc:title Early evaluation for performance enhancement in phased logic. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 24 (xsd:string)